Yesterday
Secret
Senior Level Career (10+ yrs experience)
$125,000 - $150,000
No Traveling
Engineering - Systems
Lexington, MA (On/Off-Site)
FPGA Design Engineer opportunity in Lexington, MA!
Required Skills:
-Proficient in Verilog, SystemVerilog, VHDL and C.
-Ability to take an FPGA from concept to a device that meets all functional and timing requirements. This would also include generating system level test benches to verify FPGA performance, functionality and error recovery using Mentor Questa Logic Simulator.
-Experience with the Zynq Ultrascale+ RFSoC platform.
-Experience coding across multiple clock domains.
-Experience coding triple-mode redundancy for radiation resistance.
-Familiarity with the digital processing architecture for lasercom waveform standards
-Candidate must have demonstrated knowledge of and delivered products involving:
1) the Xilinx Virtex 5 SIRF FPGA;
2) Xilinx ISE 13.2 with SIRF Overlay;
3) Synopsys Synplicity targeting the Virtex 5 SIRF;
4) Code design for radiation-hardened operation of the Xilinx Virtex 5 SIRF;
5) Radiation-hardened CPUs;
6) Analog to digital converters (ADCs) and digital to analog converters (DACs);
7) SPI, I2C, SpaceWire, and Ethernet protocols;
8) Forward error correction, including Reed-Solomon and DVB-S2;
9) CoaXPress and CameraLink camera interfaces;
10) Differential phase-shift keying (DPSK) and pulse position modulation (PPM) optical modulation techniques; and
11) Control loops for synchronization of quantum-entangled sources.
Preferred Skills:
Ability to communicate effectively with other team members. Ability to design and program a Xilinx MicroBlaze embedded processor. Familiar with Xilinx Vivado and Vivado SDK. Experience with PCIe, CoaXpress, DVBS2 Error Correction, SC-PPM FEC, and PPM modulation and demodulation is also desired.
Required Skills:
-Proficient in Verilog, SystemVerilog, VHDL and C.
-Ability to take an FPGA from concept to a device that meets all functional and timing requirements. This would also include generating system level test benches to verify FPGA performance, functionality and error recovery using Mentor Questa Logic Simulator.
-Experience with the Zynq Ultrascale+ RFSoC platform.
-Experience coding across multiple clock domains.
-Experience coding triple-mode redundancy for radiation resistance.
-Familiarity with the digital processing architecture for lasercom waveform standards
-Candidate must have demonstrated knowledge of and delivered products involving:
1) the Xilinx Virtex 5 SIRF FPGA;
2) Xilinx ISE 13.2 with SIRF Overlay;
3) Synopsys Synplicity targeting the Virtex 5 SIRF;
4) Code design for radiation-hardened operation of the Xilinx Virtex 5 SIRF;
5) Radiation-hardened CPUs;
6) Analog to digital converters (ADCs) and digital to analog converters (DACs);
7) SPI, I2C, SpaceWire, and Ethernet protocols;
8) Forward error correction, including Reed-Solomon and DVB-S2;
9) CoaXPress and CameraLink camera interfaces;
10) Differential phase-shift keying (DPSK) and pulse position modulation (PPM) optical modulation techniques; and
11) Control loops for synchronization of quantum-entangled sources.
Preferred Skills:
Ability to communicate effectively with other team members. Ability to design and program a Xilinx MicroBlaze embedded processor. Familiar with Xilinx Vivado and Vivado SDK. Experience with PCIe, CoaXpress, DVBS2 Error Correction, SC-PPM FEC, and PPM modulation and demodulation is also desired.
group id: 10107773
