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IT - Hardware
Albany, NY (On-Site/Office)
Artech is currently looking for experienced professional for the below position.
Job ID # 25-35480
Tittle: Hardware Developer Semiconductor Device Physics & Engineering
Location : Remote!
Duration : 12+ Months
Rate: $35-$40.00/hr
JD Job Duties : Basic Skills, clearances and other elements required, in order of importance, and number of years' experience, where applicable, in each skill :
1) Strong Experience with calculating and writing technology groundrules for semiconductor processing including Front End Of Line (e.g., FETs, Resistors, MOSCAPs), Middle Of Line (e.g., Contacts, Local Interconnect), and Back End Of Line (e.g., Inductors, MimCaps, Metal-to-Metal Capacitors), at least 5 years.
2) Strong understanding of physical layout and leading-edge semiconductor processing, at least 5 years
3) Experience using the Cadence Virtuoso layout design tool or other EDA layout design tool, at least 5 years.
4) Ability to debug errors and solve problems.
5) Ability to work in a team environment.
6) Fluent English (both verbal and written) and strong communication skills.
Other Skills Desired, Years in each skill, where applicable: 1) Preferred: Experience with semiconductor processing
2) Preferred: Experience with calculating and writing technology groundrules for advanced design nodes (e.g., 5nm, FinFET, Multi Patterned process, DFM).
3) Preferred: Experience using Synopsys ICV DRC and LVS tool.
4) Preferred: Experience with Python, other scripting languages, for automation.
Please apply on our company website (www.artechinfo.com) with reference to job ID, or contact me at pooja.choudhary@artech.com for more details regarding position including feedback.
Job ID # 25-35480
Tittle: Hardware Developer Semiconductor Device Physics & Engineering
Location : Remote!
Duration : 12+ Months
Rate: $35-$40.00/hr
JD
- Job Duty 1 - Calculating and writing technology groundrules for semiconductor processing.
- Job Duty 2 - Review and Debug manual layout and DRC checking results.
- Job Duty 3 - Work closely with Process Integration and Patterning leads to define required technology design rules.
- Job Duty 4 - Evaluate and disposition design waivers for testsite macro design.
- Job Duty 5 - Aid in development of standards and groundrule automation creation.
1) Strong Experience with calculating and writing technology groundrules for semiconductor processing including Front End Of Line (e.g., FETs, Resistors, MOSCAPs), Middle Of Line (e.g., Contacts, Local Interconnect), and Back End Of Line (e.g., Inductors, MimCaps, Metal-to-Metal Capacitors), at least 5 years.
2) Strong understanding of physical layout and leading-edge semiconductor processing, at least 5 years
3) Experience using the Cadence Virtuoso layout design tool or other EDA layout design tool, at least 5 years.
4) Ability to debug errors and solve problems.
5) Ability to work in a team environment.
6) Fluent English (both verbal and written) and strong communication skills.
2) Preferred: Experience with calculating and writing technology groundrules for advanced design nodes (e.g., 5nm, FinFET, Multi Patterned process, DFM).
3) Preferred: Experience using Synopsys ICV DRC and LVS tool.
4) Preferred: Experience with Python, other scripting languages, for automation.
Please apply on our company website (www.artechinfo.com) with reference to job ID, or contact me at pooja.choudhary@artech.com for more details regarding position including feedback.
group id: artech
