Today
Top Secret/SCI
Unspecified
Polygraph
IT - QA and Test
Linthicum, MD (On-Site/Office)
R-00147620
Description
Leidos is currently looking to add a Test and Integration Engineer to a Cyber Security Program near Ft. Meade, MD. This challenging position supports a complex, mission-critical Program. The successful candidate will perform the installation, integration, and test of operational equipment/software to verify compliance with the system design, requirements, and standards. Perform in-depth security verification testing of cryptographic product designs and equipment.
CLEARANCE REQUIRED : Active TS/SCI w/ Polygraph.
Primary Responsibilities
Basic Qualifications
CONMD
Original Posting Date: 2024-11-05
While subject to change based on business needs, Leidos reasonably anticipates that this job requisition will remain open for at least 3 days with an anticipated close date of no earlier than 3 days after the original posting date as listed above.
Pay Range: Pay Range $126,100.00 - $227,950.00
The Leidos pay range for this job level is a general guideline only and not a guarantee of compensation or salary. Additional factors considered in extending an offer include (but are not limited to) responsibilities of the job, education, experience, knowledge, skills, and abilities, as well as internal equity, alignment with market data, applicable bargaining agreement (if any), or other law.
Description
Leidos is currently looking to add a Test and Integration Engineer to a Cyber Security Program near Ft. Meade, MD. This challenging position supports a complex, mission-critical Program. The successful candidate will perform the installation, integration, and test of operational equipment/software to verify compliance with the system design, requirements, and standards. Perform in-depth security verification testing of cryptographic product designs and equipment.
CLEARANCE REQUIRED : Active TS/SCI w/ Polygraph.
Primary Responsibilities
- Prepare interactive Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) test benches.
- Write test scripts using “C” and “Tcl/TK” code languages.
- Conduct functional verification and testing of new ASIC designs prior to fabrication using Field Programmable Gate Arrays (FPGA) to emulate the chips.
- (U//FOUO) Write custom interfaces between Commercial off the Shelf (COTS) software and Mentor Graphics products.
- Use advanced verification methodologies using industry standard UVM (Unified Verification Methodology).
- Perform functional testing on variants, prototype devices and production versions of ASIC chip designs following production.
- Design in-depth security verification tests
Basic Qualifications
- Active TS/SCI w/ Polygraph
- Ten (10+) years of IA hardware testing and integration development experience and an Engineering or Computer Science Bachelor’s degree. An additional four (4) years of experience may be substituted for the education requirement.
- Ten (10+) years of experience in the following applicable programming languages: Java, Python, C/C++, RISC Assembly, Bash, Tcl/TK, and Verilog.
- Ten (10+) years of experience with GitLab, FPGA design, Xilinx's Vivado, Microblaze Design Suite, and Partial Reconfiguration.
CONMD
Original Posting Date: 2024-11-05
While subject to change based on business needs, Leidos reasonably anticipates that this job requisition will remain open for at least 3 days with an anticipated close date of no earlier than 3 days after the original posting date as listed above.
Pay Range: Pay Range $126,100.00 - $227,950.00
The Leidos pay range for this job level is a general guideline only and not a guarantee of compensation or salary. Additional factors considered in extending an offer include (but are not limited to) responsibilities of the job, education, experience, knowledge, skills, and abilities, as well as internal equity, alignment with market data, applicable bargaining agreement (if any), or other law.
group id: SCNCAPI2
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